This invention relates to a synchronizing circuit which generates a signal synchronizing with an external clock signal and is applied to, for example, a synchronous DRAM.
One known circuit for generating an internal clock signal synchronizing with an external clock signal is a SAD (Synchronous Adjustable Delay) synchronizing circuit. This type of synchronizing circuit supplies an external clock signal to a first delay line composed of unit delay elements without using a feedback loop. The period of the clock signal transferred to the first delay line is measured directly. Information on the measured period is stored in a state holding section. On the basis of the information stored in the state holding section, a new clock signal is supplied to a second delay line composed of unit delay elements. This produces a clock signal which synchronizes with the external clock and lags behind by an integral multiple of the period from the external clock signal.
In this type of synchronizing circuit, the accuracy with which the internal clock signal synchronizes with the external clock signal depends on the amount of delay in the unit delay elements. To transfer data at high speed, it is necessary to increase the frequency of the clock signal. When the frequency of the clock signal has increased to such an extent that it cannot be ignored as compared with the amount of delay in the unit delay elements, the accuracy of synchronization can decrease.
It is, accordingly, an object of the present invention to overcome the above problem by providing a synchronizing circuit capable of improving the accuracy of synchronization even when the frequency of the clock has increased.
The foregoing object is accomplished by providing a synchronizing circuit comprising: a first delay line which includes unit delay elements and transfers a forward pulse signal; a second delay line which includes unit delay elements and transfers a backward pulse signal; and a state holding section which senses the transfer position of the forward pulse signal transferred along the first delay line and controls the backward pulse signal transferred along the second delay line, wherein each of the unit delay elements constituting the first and second delay lines has transistors including first and second transistors, the current driving capability of the first transistors being set higher than that of the second transistors, the first transistors making a response when the signal inputted to the unit delay elements changes from a first level to a second level higher than the first level, and the second transistors making a response when the signal inputted to the unit delay elements changes from the second level to the first level.
With the present invention, the current driving capability of the transistors related to the rising of the pulse signal in the unit delay elements is increased. As a result, the rise time of the pulse signal is made shorter, which improves the accuracy of synchronization, even when the frequency of the clock signal gets higher. In addition, the pulse width of the signal passed through the unit delay elements can be kept constant.
The foregoing object is also accomplished by providing a synchronizing circuit comprising: a first delay line which includes unit delay elements and transfers a forward pulse signal; a second delay line which includes as many unit delay elements as equals half the number of the unit delay elements the first delay line has and which transfers a backward pulse signal; and a state holding section including state holding circuits arranged so as to correspond to the unit delay elements constituting the first and second delay lines, the state holding circuits being set by the forward pulse signal transferred along the first delay line and reset by the backward pulse signal transferred along the second delay line and having a set state in which a pair of adjacent ones of the state holding circuits have been set, a reset state in which a pair of adjacent ones of the state holding circuits have been reset, and an intermediate state in which one of a pair of adjacent ones of the state holding circuits is set and the other of the pair is reset.
With the present invention, the accuracy of synchronization can be improved to half the amount of delay in a unit delay element and a clock signal delayed for half the period can be generated from the inputted clock signal.
Furthermore, the foregoing object is accomplished by providing a synchronizing circuit comprising: a first delay line which includes unit delay elements and transfers a forward pulse signal; a second delay line which includes unit delay elements and transfers a backward pulse signal; and a state holding section including state holding circuits arranged so as to correspond to the unit delay elements constituting the first delay line, the state holding circuits being set according to the forward pulse signal transferred along the first delay line and reset according to the backward pulse signal transferred along the second delay line and having a set state in which n adjacent ones (n is an integer equal to or larger than 2) of the state holding circuits have all been set, a reset state in which all of the n adjacent state holding circuits have been reset, and (nxe2x88x921) intermediate states in which the n adjacent state holding circuits are either set or reset.
With the present invention, the second clock signal is synchronized with the first clock signal with the accuracy of synchronization of {fraction (1/n)} the amount of delay in a unit delay element, which improves the accuracy of synchronization.
Still furthermore, the foregoing object is accomplished by providing a synchronizing circuit comprising: n division circuits for dividing a first clock signal into n signals with an n-fold period (n is an integer equal to or larger than 2); n synchronizing circuits to which the signals divided by the n division circuits are supplied respectively; and a generator circuit for combining the output signals of the n synchronizing circuits and producing a second clock signal with the same period as that of the first clock signal.
With the present invention, the second clock signal is synchronized with the first clock signal with the accuracy of synchronization of {fraction (1/n)} the amount of delay in a unit delay element. This makes it possible to improve the accuracy of synchronization more, even when the frequency of the clock signal gets higher.
Moreover, the foregoing object is accomplished by providing a delay circuit comprising: a clocked inverter circuit to which an input pulse signal is supplied; and a logic circuit to which a pulse signal outputted from the clocked inverter circuit and the inverted signal of the input pulse signal are supplied, wherein the clocked inverter circuit changes the pulse width of the input pulse signal in the direction opposite to the direction in which the pulse width of the pulse signal outputted from the logic circuit changes.
In the present invention, the delay circuit is composed of a circuit for widening the pulse width and a circuit for narrowing the pulse width, which prevents the pulse width from getting narrower.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.